The present invention relates to reticle based skew lots. More particularly, the present invention relates to generating skew lots on a single semiconductor wafer by using a reticle that has different magnitudes of a critical dimension, e.g., gate length.
High density integrated circuits are currently mass-produced with several critically-dimensioned features, e.g., transistor gate length, channel width, trench depth, etc. FIG. 1 shows a portion of a partially fabricated die 10 including an "L" shaped gate electrode 14 of a Metal Oxide Semiconductor (MOS) transistor device on a substrate 12 having a length 16 (labeled as ".lambda." and hereafter referred to as gate length). It is well known to those skilled in the art that gate length 16 is primarily responsible for determining the maximum transistor switching speed, overall device operating speed and performance of the transistor device. By way of example, the gate length 16 in a 0.25 .mu.m technology is ideally about 0.25 .mu.m and similarly in a 0.35 .mu.m technology is ideally about 0.35 .mu.m.
However, due to process variations during a semiconductor fabrication process, for example, gate length 16 may frequently vary from the ideal or target gate length value of 0.35 .mu.m to gate lengths that may be as low as about 0.30 .mu.m and may be as high as about 0.40 .mu.m or more. It is, therefore, desirable to produce die having gate lengths within a tolerance range, i.e. the range of deviation of an actual gate length from the target gate length that allows the transistor device to function effectively and have speeds above an acceptable threshold.
In order to ensure that deviations from the target value of the gate length do not adversely impact the speed or performance of the transistor and fall below the acceptable threshold, the semiconductor fabrication facilities or their customers, e.g., users of die or semiconductor chips, generate wafer skew lots or process corner lots. The term "wafer lot" commonly refers to wafers that are secured on a wafer cassette and processed together under relatively similar conditions. The term "wafer skew lots," as used in connection with the description of this invention, refers to a plurality of wafer lots, in which the value of a critical dimension, varies from one wafer lot to another. In order to produce a different gate length, for example, the wafer lot is processed under different processing conditions or employs a different reticle during a masking step. In other words, in wafer skew lots, a critical dimension, such as a transistor gate length, is skewed from one wafer lot to another to characterize the performance and speed of the transistor devices at different values of the critical dimension.
The term "process corner lots" refers to wafer lots that have gate lengths at various process corners, which are explained in detail hereinafter. As mentioned above, the gate length from one wafer lot to another may purposely be varied to reflect the variations produced by the process during commercial wafer production. By way of example, one wafer lot is processed so that its transistor gate lengths have little or no difference from the target gate length and such processing of the wafer lot may be characterized in the semiconductor art as being conducted at a "typical" or "nominal" process point. As another example, another wafer lot may be processed to have the largest gate length encountered due to process variations relative to the target gate length, e.g., about 10% larger than the target gate length, and the processing of this wafer lot may be characterized in the art as being conducted at a "worst" case point. As yet another example, yet another wafer lot may be processed to have the smallest gate lengths encountered due to process variations relative to the target gate length, e.g., about 10% smaller than the target gate length, and the processing of this wafer lot may be characterized as being conducted at a "best" case point. Process corners are, therefore, the various process points, e.g., nominal or typical process point, worst case point and best case point and process corner lots refer to wafer lots processed at these various process corners.
FIG. 2 is a flowchart of a current process 20 of fabricating wafer skew lots or process corner lots using different reticles. Before process 20 begins, a gate oxide layer, e.g., silicon dioxide layer, is typically grown on the wafer surfaces of a wafer lot. A step 22 includes blanket depositing a gate layer, e.g., a polysilicon layer, above the wafer surfaces of a wafer lot according to conventional methods well known to those skilled in the art.
Next a step 24 includes obtaining conventional reticles employed during photolithography to define masks which protect specified regions of a semiconductor wafer from etching. A reticle used in this step includes patterns defining gate electrodes, which have identical values of a critical dimension, such as a gate length, throughout the reticle and the gate lengths on the reticle may target a specific process corner, e.g., nominal process point, worst case point or best case point. The wafers in a wafer lot are processed using the same reticle and may therefore have gate lengths that are similar from die to die on the wafer surfaces of the wafer lot. However, the gate lengths vary from one wafer lot to another because a different reticle is employed for a different wafer lot. In subsequent steps of process 20, the pattern of the reticle employed is transferred on the gate layer by conventional photolithography techniques described below.
A step 26 then includes forming a gate mask on portions of the gate layer using the conventional reticle mentioned above. In this step, a masking layer, e.g., a photoresist layer, is typically deposited on the gate layer. A light source, e.g., ultraviolet light source, then shines through the reticle on to the wafer surface to form on the gate layer a mask having the image of the gate electrode pattern (hereinafter referred to as "gate mask") of the reticle. As a result, the dimensions of the gate mask formed in this step are dictated by the specific process corner targeted by the reticle.
A step 28 includes etching the unmasked portions of the gate layer to form gate electrodes on wafers. In this step, etchants are introduced on the wafer surface to facilitate etching of the unmasked portions of the gate layer or the wafer is placed in a plasma chamber where the unmasked portions of the gate layer undergo dry etching. After, etching has concluded, the photoresist remaining above the protected portions is removed by wet chemistry or ashing. In this manner, different reticles that target different process corners can be used for fabricating wafer skew lots, e.g., one wafer lot is processed at the nominal point, another wafer lot is processed at the worse case point and yet another wafer lot is processed at the best case point.
After the skewed wafer lots are fabricated as described above, they are tested to characterize device speed and performance at the various process corners, e.g. nominal, worse and best case points. This enables the semiconductor fabrication facility or the end user of the die to understand the interaction of the device with other devices on a printed circuit board or system and ascertain the best case performance of the device.
Unfortunately, the process of generating skewed wafer lots suffers from several drawbacks. By way of example, the process of generating skewed wafer lots described above is expensive because it requires fabricating a wafer lot for each process corner. For example, if the nominal, best and worse case points are under consideration, then three wafer lots are processed (one wafer lot for each process corner). This can also be a time-consuming task, lowering the throughput of the semiconductor fabrication process.
As another example, one wafer lot is typically run separately from another and therefore it is likely that a variable affecting the performance of one wafer lot and not the other may be introduced. In this case, of course, it would difficult to correlate the speed or performance of the device to its gate length alone.
As yet another example, in the case where a process is biased to form a gate length that varies from the ideal or target gate length, variations in the process cannot ensure that the desired gate length will be produced.
What is therefore needed is an improved process of generating skew lots without suffering from the drawbacks of the current process of generating wafer skew lots.